Multi-level circuits for use with transducers, such as ultrasound transducer are well known in the art. Referring to FIG. 1a there is shown a circuit diagram of a multi-level (five level) transmitter circuit 10 of the prior art. The circuit 10 has an output node 14 for connection to a transducer 12. The transducer 12, can be any type of capacitive transducer, such as ultrasound, MEMS, piezoelectric or any other type of capacitive transducer. The transducer 12 is connected between the output node 14 and ground. The circuit 10 receives as its inputs six input signals having voltages designated as VINP0, VINP1, VINPG, VINNG, VINN1, and VINN0. Four of the six input signals are supplied to a level shifter 20, the details of which are shown in FIG. 2. The level shifter 20 simply shifts the voltage of the input signal to a higher voltage. The input signals VINPG and VINNG are supplied to the circuit 10 directly without going through a level shifter 20.
The circuit 10 has six voltage paths. A first voltage path extends from a voltage source HVP0 to node 14. A second voltage path extends from a voltage source HVP1 to node 14. A third voltage path extends from ground to node 14. A fourth voltage path extends from a voltage source HVN0 to node 14. A fifth voltage path extends from a voltage source HVN1 to node 14. A sixth voltage path extends from ground to node 14.
The first voltage path has a PMOS transistor 22 connected between HVP0 and node 14. The voltage HVP0 is a positive voltage. The transistor 22 is activated by the signal from the output of the voltage level shifter 20a, whose input is the input signal VINP0. The second voltage path has a PMOS transistor 24 connected between HVP1 and a diode 26 to the node 14. The voltage HVP1 is a positive voltage but is less positive than the voltage HVP0. The transistor 24 is activated by the signal from the output of the voltage level shifter 20b, whose input is the input signal VINP1. The third voltage path has a PMOS transistor 28 connected between ground and a diode 30 to the node 14. The transistor 28 is activated by the input signal VINPG. The level shifters 20a and 20b are identical and are shown in FIG. 2.
The fourth voltage path has a NMOS transistor 32 connected between HVN0 and node 14. The voltage HVN0 is a negative voltage. The transistor 32 is activated by the signal from the output of the voltage level shifter 20d, whose input is the input signal VINN0. The fifth voltage path has a NMOS transistor 34 connected between HVN1 and a diode 36 to the node 14. The voltage HVN1 is a negative voltage but is less negative than the voltage HVN0. The transistor 34 is activated by the signal from the output of the voltage level shifter 20c, whose input is the input signal VINN1. The sixth voltage path has a NMOS transistor 38 connected between ground and a diode 40 to the node 14. The transistor 38 is activated by the input signal VINNG. The level shifters 20c and 20d are identical and are shown in FIG. 2.
The difference in the voltage of the voltage sources HVP0, HVP1, Ground, HVN1 and HVN0 is graphically shown in FIG. 1b. This gives rise to the transmitter circuit 10 producing a multi-level output at the node 14.
One of the problems with the circuit 10 of the prior art is that for different voltage input signals, the different voltage outputs at node 14 results, with the output node 14 having different output impedances. Therefore, it is desired that the output impedance for the different output levels should all have approximately the same impedance. One prior art method to avoid impedance mismatch is to use a two level driver with proper termination and complex binary codes. Although the reduction of the number of levels results in reduction in impedance mismatch, and also reduces costs and saves real estate and facilitates design, it comes at the expense of reduction of resolution and penetration of the transducer 12. Hence there is a need to reduce impedance mismatch for a multi-level transmitter circuit.